Silicon Product and Test Engineer

About the Role You will drive post silicon productization of bitcoin mining ASICs from silicon bring-up through high-volume manufacturing. You will perform silicon characterization, yield optimization, test strategy development, and cross-functional collaboration with design, ATE, reliability, and OSAT partners. You will analyze data from CP FT Bench and System, define DOE plans, and develop dashboards to monitor power, performance, and quality.

Requirements Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. 5–10 years of experience in Product Engineering, Test Engineering, Silicon Validation, or Post-Silicon Engineering in fabless or semiconductor environments. Strong understanding of semiconductor manufacturing flows including wafer sort (CP), final test (FT), qualification, and high-volume manufacturing. Experience with silicon bring-up, characterization, yield analysis, and product qualification for advanced-node ASICs or SoCs. Experience with ATE platforms such as Advantest 93K or Chroma. Experience developing or debugging ATE test programs and production screening methodologies. Strong statistical data analysis and debugging skills using tools such as JMP, Python, or similar analysis frameworks. Experience with DOE planning, silicon correlation, and yield optimization methodologies. Experience collaborating cross-functionally across Design, Systems, Firmware, Reliability, Manufacturing, Foundry, and OSAT teams. Strong problem-solving skills with the ability to independently drive technical issues to closure. Comfortable operating in ambiguous, fast-moving environments with a high degree of ownership. Experience with near-threshold operation or low-voltage optimization. Experience with high-performance computing, AI, networking, or bitcoin mining ASICs. Understanding of semiconductor device physics, SPICE fundamentals, and FinFET technologies. Experience with system-level characterization and correlation across ATE, Bench, and deployed systems. Experience with scripting or automation using Python, Perl, or TCL. Verbal fluency in Mandarin is a plus.

Responsibilities Drive post-silicon bring-up, characterization, qualification, and productization activities from first silicon through mass production. Develop and optimize wafer sort (CP) and final test (FT) screening strategies to improve power, performance, yield, quality, and DPPM. Develop, debug, and maintain ATE test programs and screening methodologies for advanced-node ASICs. Define and execute characterization plans across process, voltage, and temperature (PVT) conditions. Perform silicon data analysis across CP, FT, Bench, and System platforms to improve correlation and optimize system-level performance. Drive DOE planning, execution, and analysis for silicon characterization, yield optimization, and process tuning. Collaborate with system and hardware engineers to develop effective ASIC binning methodologies and system optimization strategies. Define and support ATE hardware requirements including probe cards, sockets, and load boards. Analyze wafer-level and package-level parametric and functional data to identify trends, root-cause failures, and drive corrective actions. Engage with foundry, OSAT, and external vendors to support bring-up, qualification, yield improvement, and manufacturing execution. Develop KPIs and dashboards to track power, performance, process variation, yield, and product quality metrics.

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