Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will lead and scale digital design across RTL, integration, and methodology. You will translate architecture into RTL, own logical design through tape-out, coordinate with verification and physical design, enforce quality practices, support silicon bring-up, and develop engineers.
Requirements
- Extensive digital or logical design experience for complex SoCs with multiple tape-outs
- Ability to lead and grow silicon design teams
- Expertise in RTL and micro-architecture development using SystemVerilog or Verilog
- Experience with large-scale SoC integration including CPUs, accelerators, memory subsystems, and interconnects
- Understanding of performance, power, and area trade-offs in advanced process nodes
- Experience working with verification and physical design teams to achieve functional and timing closure
- Communication skills
Responsibilities
- Lead and grow the silicon logical design team across RTL, integration, and methodology
- Translate system and micro-architecture specifications into RTL implementations
- Own end-to-end logical design execution from concept through tape-out
- Partner with architecture, verification, physical design, DFT, software, and product functions
- Define and enforce RTL quality, coding, reuse, and design-review practices
- Oversee block-level and top-level integration against performance, power, area, and schedule targets
- Support bring-up, debug, silicon validation, and root-cause analysis
- Contribute to technology roadmap planning and IP strategy
- Mentor and develop engineers
Benefits
- Pension plan
- Employee insurances
- Company shares